It is often desirable to provide improved accessibility to specific areas of an integrated circuit or a group of integrated circuits installed in a surface mount technology (SMT) or other high density environment (TAB, PCB ) that allows the user to test and verify proper operation of a particular IC or path without any modification of the hardware or additional physical connections to the circuits or to the system the circuits reside in. The test access hardware should not affect the normal operation of the circuits or create additional delays or performance problems, and should be done nonintrusively so that the individual integrated circuits and the system can be tested while installed in an operational environment. The need for this kind of testability access led to the development of boundary scan techniques which allow access to the pins of the integrated circuits without intrusive test hardware. The need to test integrated circuits manufactured by different vendors in a system environment further led to the development of a standard testability bus for boundary scan applications, the JTAG (Joint Test Action Group) standard bus. The JTAG bus is now governed by IEEE standard 1149.1.
A designer who wishes to build boundary scan testing into a circuit board, integrated circuit or system and use the JTAG bus must first implement the boundary scan path and configure it for the particular application or system. This task becomes particularly difficult when the designer intends to use memories or other off-the-shelf components which are not JTAG compatible. The high cost of designing hardware or a custom integrated circuit for a particular application, coupled with the amount of time required to design, test and fabricate such hardware or customized integrated circuits creates a need for a general purpose, universal, programmable integrated circuit device which can be used to implement and test boundary scan paths using the JTAG bus for any application.
Without limiting the scope of the invention, its background is described in connection with boundary scan techniques used to test and communicate with integrated circuit devices (ICs) not having built-in boundary scan capabilities. Although the particular embodiment presupposes the use of the JTAG standard bus, alternative communication arrangements can be used, as will be obvious to one experienced in the art.
Heretofore, in this field, various boundary scan techniques have been used by system designers. However, each designer has had to implement a scan bus specifically designed for each application. The time and cost of designing, testing and manufacturing hardware or custom integrated circuits for each system is prohibitive. Further, the use of several different systems in one operating environment, each system having a different boundary scan methodology, results in reduced capability and creates a need for additional translation hardware or bus couplers which require additional design and test time and may reduce overall system performance.